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1/19 july 2002 M48T02 m48t12 5.0v, 16 kbit (2kb x 8) timekeeper ? sram features summary n integrated, ultra low power sram, real time clock, and power-fail control circuit n bytewide? ram-like clock access n bcd coded year, month, day, date, hours, minutes, and seconds n typical clock accuracy of 1 minute a month, at 25c n software controlled clock calibration for high accuracy applications n automatic power-fail chip deselect and write protection n write protect voltages (v pfd = power-fail deselect voltage): C M48T02: v cc = 4.75 to 5.5v 4.5v v pfd 4.75v C m48t12: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v n self-contained battery and crystal in the caphat? dip package n pin and function compatible with jedec standard 2k x 8 srams figure 1. 24-pin pcdip, caphat? package 24 1 pcdip24 (pc) battery/crystal caphat
M48T02, m48t12 2/19 table of contents summarydescription...........................................................3 logicdiagram(figure2.).........................................................3 signalnames(table1.)..........................................................3 dip connections (figure 3.) .......................................................3 blockdiagram(figure4.).........................................................4 maximumrating.................................................................4 absolutemaximumratings(table2.) ...............................................4 dc and ac parameters. . ........................................................5 operating and ac measurement conditions (table 3.) ..................................5 ac testing load circuit (figure 5.) ..................................................5 capacitance (table 4.) . . . ........................................................5 dccharacteristics(table5.) ......................................................6 operationmodes...............................................................6 operating modes (table 6.) ........................................................6 readmode....................................................................7 readmodeacwaveforms(figure6.)..............................................7 readmodeaccharacteristics(table7.)............................................7 writemode...................................................................8 write enable controlled, write ac waveform (figure 7.) ..............................8 chipenablecontrolled,writeacwaveforms(figure8.)...............................8 writemodeaccharacteristics(table8.) ...........................................9 dataretentionmode............................................................10 checkingthebokflagstatus(figure9.) ...........................................10 powerdown/upmodeacwaveforms(figure10.) ....................................11 powerdown/upaccharacteristics(table9.)........................................11 powerdown/uptrippointsdccharacteristics(table10.)..............................11 clockoperations.............................................................12 reading the clock . .............................................................12 settingtheclock...............................................................12 registermap(table11.).........................................................12 stopping and starting the oscillator ................................................13 calibratingtheclock............................................................13 crystalaccuracyacrosstemperature(figure11.) ....................................14 clockcalibration(figure12.) .....................................................14 v cc noise and negative going transients . ..........................................15 supplyvoltageprotection(figure13.)..............................................15 partnumbering ...............................................................16 package mechanical information . . . ..........................................17 revisionhistory...............................................................18
3/19 M48T02, m48t12 summary description the M48T02/12 timekeeper ? ram is a 2kb x 8 non-volatile static ram and real time clock which is pin and functional compatible with the ds1642. a special 24-pin, 600mil dip caphat? package houses the M48T02/12 silicon with a quartz crystal and a long life lithium button cell to form a highly integrated battery backed-up memory and real time clock solution. the M48T02/12 button cell has sufficient capacity and storage life to maintain data and clock func- tionality for an accumulated time period of at least 10 years in the absence of power over the operat- ing temperature range. the M48T02/12 is a non-volatile pin and function equivalent to any jedec standard 2kb x 8 sram. it also easily fits into many rom, eprom, and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. figure 2. logic diagram table 1. signal names figure 3. dip connections ai01027 11 a0-a10 w dq0-dq7 v cc M48T02 m48t12 g v ss 8 e a0-a10 address inputs dq0-dq7 data inputs / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground a1 a0 dq0 a7 a4 a3 a2 a6 a5 a10 a8 a9 dq7 w g e dq5 dq1 dq2 dq3 v ss dq4 dq6 v cc ai01028 M48T02 m48t12 8 1 2 3 4 5 6 7 9 10 11 12 16 15 24 23 22 21 20 19 18 17 14 13
M48T02, m48t12 4/19 figure 4. block diagram maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. ai01329 lithium cell oscillator and clock chain v pfd v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 biport sram array 2040 x 8 sram array a0-a10 dq0-dq7 e w g power bok symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (2) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7 v v cc supply voltage C0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
5/19 M48T02, m48t12 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 5. ac testing load circuit table 4. capacitance note: 1. effective capacitance measured with power supply at 5v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter M48T02 m48t12 unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 100 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k w device under test 1k w symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
M48T02, m48t12 6/19 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. outputs deselected. 3. measured with control bits set as follows: r = '1'; w, st, ft = '0.' 4. negative spikes of C1v allowed for up to 10ns once per cycle. operation modes as figure 4, page 4 shows, the static memory ar- ray and the quartz controlled clock oscillator of the M48T02/12 are integrated on one silicon chip. the two circuits are interconnected at the upper eight memory locations to provide user accessible bytewide? clock information in the bytes with addresses 7f8h-7ffh. the clock locations con- tain the year, month, date, day, hour, minute, and second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. byte 7f8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport? read/write memory cells. the M48T02/12 includes a clock control cir- cuit which updates the clock bytes with current in- formation once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the M48T02/12 also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5v supply for an out of tolerance condi- tion. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc .asv cc falls be- low approximately 3v, the control circuitry con- nects the battery which maintains data and clock operation until valid power returns. table 6. operating modes note: x = v ih or v il ;v so = battery back-up switchover voltage. 1. see table 10, page 11 for details. symbol parameter test condition (1) min max unit i li input leakage current 0v v in v cc 1 a i lo (2) output leakage current 0v v out v cc 1 a i cc supply current outputs open 80 ma i cc1 (3) supply current (standby) ttl e =v ih 3ma i cc2 (3) supply current (standby) cmos e =v cc C 0.2v 3ma v il (4) input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = C1ma 2.4 v mode v cc e g w dq0-dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
7/19 M48T02, m48t12 read mode the M48T02/12 is in the read mode whenever w (write enable) is high and e (chip enable) is low. the device architecture allows ripple-through access of data from eight of 16,384 locations in the static storage array. thus, the unique address specified by the 11 address inputs defines which one of the 2,048 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 6. read mode ac waveforms note: write enable (w )=high. table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). symbol parameter (1) M48T02/m48t12 unit C70 C150 C200 min max min max min max t avav read cycle time 70 150 200 ns t avqv address valid to output valid 70 150 200 ns t elqv chip enable low to output valid 70 150 200 ns t glqv output enable low to output valid 35 75 80 ns t elqx chip enable low to output transition 5 10 10 ns t glqx output enable low to output transition 5 5 5 ns t ehqz chip enable high to output hi-z 25 35 40 ns t ghqz output enable high to output hi-z 25 35 40 ns t axqx address transition to output transition 10 5 5 ns ai01330 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a10 e g dq0-dq7 valid
M48T02, m48t12 8/19 write mode the M48T02/12 is in the write mode whenever w and e are active. the start of a write is refer- enced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for aminimumoft ehax from chip enable or t whax from write enable prior to the initiation of anoth- er read or write cycle. data-in must be valid t d- vwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g ,alowonw will disable the outputs t wlqz after w falls. figure 7. write enable controlled, write ac waveform figure 8. chip enable controlled, write ac waveforms ai01331 tavav twhax tdvwh data input a0-a10 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01332b tavav tehax tdveh a0-a10 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
9/19 M48T02, m48t12 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). symbol parameter (1) M48T02/m48t12 unit C70 C150 C200 min max min max min max t avav write cycle time 70 150 200 ns t av wl address valid to write enable low 0 0 0 ns t av el address valid to chip enable low 0 0 0 ns t wlwh write enable pulse width 50 90 120 ns t eleh chip enable low to chip enable high 55 90 120 ns t whax write enable high to address transition 0 10 10 ns t ehax chip enable high to address transition 0 10 10 ns t dvwh input valid to write enable high 30 40 60 ns t dveh input valid to chip enable high 30 40 60 ns t whdx write enable high to input transition 5 5 5 ns t ehdx chip enable high to input transition 5 5 5 ns t wlqz write enable low to output hi-z 25 50 60 ns t avwh address valid to write enable high 60 120 140 ns t ave h address valid to chip enable high 60 120 140 ns t whqx write enable high to output transition 5 10 10 ns
M48T02, m48t12 10/19 data retention mode with valid v cc applied, the M48T02/12 operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high imped- ance, and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the M48T02/12 may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. the power switching circuit connects external v cc to the ram and disconnects the battery when v cc rises above v so .asv cc rises, the battery voltage is checked. if the voltage is too low, an internal battery not ok (bok ) flag will be set. the bok flag can be checked after power up. if the bok flag is set, the first write attempted will be blocked. the flag is automatically cleared after the first write, and normal ram operation resumes. fig- ure 9 illustrates how a bok check routine could be structured. for more information on a battery storage life re- fer to the application note an1012. figure 9. checking the bok flag status read data at any address ai00607 is data complement of first read? (battery ok) power-up yes no write data complement back to same address read data at same address again notify system of low battery (data may be corrupted) write original data back to same address (battery low) continue
11/19 M48T02, m48t12 figure 10. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e high as v cc rises past v pfd (min). some systems may perform inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begin. even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running. table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than tf may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a =0to70c;v cc = 4.75 to 5.5v or 4.5 to 5.5v (except where noted). 3. at 25c. symbol parameter (1) min max unit t pd e or w at v ih before power down 0s t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 0s t rb v ss to v pfd (min) v cc rise time 1s t rec e or w at v ih before power up 2ms symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage M48T02 4.5 4.6 4.75 v m48t12 4.2 4.3 4.5 v v so battery back-up switchover voltage 3.0 v t dr (3) expected data retention time 10 years ai00606 v cc inputs (per control input) outputs don't care high-z tf tfb tr trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so
M48T02, m48t12 12/19 clock operations reading the clock updates to the tim ekeeper ? registers should be halted before clock data is read to prevent reading data in transition. the biport? time- keeper cells in the ram array are only data reg- isters and not the actual clock counters, so updating the registers can be halted without dis- turbing the clock itself. updating is halted when a '1' is written to the read bit, the seventh bit in the control register. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper registers are updated si- multaneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0.' setting the clock the eighth bit of the control register is the write bit. setting the write bit to a '1,' like the read bit, halts updates to the time keeper registers. the user can then load them with the correct day, date, and time data in 24 hour bcd format (on ta- ble 11). resetting the write bit to a '0' then trans- fers the values of all time registers (7f9-7ff) to the actual timekeeper counters and allows nor- mal operation to resume. the ft bit and the bits marked as '0' in table 11 must be written to '0' to allow for normal timekeeper and ram opera- tion. see the application note an923, timek eeper ? rolling into the 21 st century for information on century rollover. table 11. register map keys: s = sign bit ft = frequency test bit (set to '0' for normal clock operation) r = read bit w=writebit st = stop bit 0=mustbesetto'0' address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 7ff 10 years year year 00-99 7fe 0 0 0 10 m month month 01-12 7fd 0 0 10 date date date 01-31 7fc 0 ft 0 0 0 day day 01-07 7fb 0 0 10 hours hours hours 00-23 7fa 0 10 minutes minutes minutes 00-59 7f9 st 10 seconds seconds seconds 00-59 7f8 w r s calibration control
13/19 M48T02, m48t12 stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is the msb of the seconds register. setting it to a '1' stops the oscillator. the M48T02/12 is shipped from stmicroelectronics with the stop bit set to a '1.' when reset to a '0,' the M48T02/12 oscillator starts within one second. calibrating the clock the M48T02/12 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 hz. a typical M48T02/12 is accurate within 1 minute per month at 25c without calibration. the devices are tested not to exceed 35 ppm (parts per mil- lion) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. the oscillation rate of any crystal changes with temperature. figure 11, page 14 shows the fre- quency error that can be expected at various tem- peratures. most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. the M48T02/12 design, however, employs periodic counter cor- rection. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 12, page 14. the number of times pulses are blanked (subtract- ed, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit calibration byte found in the control register. adding counts speeds the clock up, sub- tracting counts slows the clock down. the calibration byte occupies the five lower order bits in the control register. this byte can be set to represent any value between 0 and 31 in binary form. the sixth bit is the sign bit; '1' indicates pos- itive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or C2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is in fact running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. two methods are available for ascertaining how much calibration a given M48T02/12 may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accu- rate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his en- vironment may require, even after the final product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of some test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is running at 32,768 hz, the lsb (dq0) of the seconds reg- ister will toggle at 512 hz. any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for exam- ple, a reading of 512.01024 hz would indicate a +20 ppm oscillator frequency error, requiring a C 10 (wr001010) to be loaded into the calibration byte for correction. note: setting or changing the calibration byte does not affect the frequency test output fre- quency. the device must be selected and ad- dresses must be stable at address 7f9 when reading the 512 hz on dq0. the ft bit must be set using the same method used to set the clock: using the write bit. the lsb of the seconds register is monitored by hold- ing the M48T02/12 in an extended read of the seconds register, but without having the read bit set. the ft bit must be reset to '0' for normal clock operations to resume. note: it is not necessary to set the write bit when setting or resetting the frequency test bit (ft) or the stop bit (st). for more information on calibration, see the appli- cation note an924, timek eeper ? calibration.
M48T02, m48t12 14/19 figure 11. crystal accuracy across temperature figure 12. clock calibration ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c ai00594b normal positive calibration negative calibration
15/19 M48T02, m48t12 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sultinginspikesonthev cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (as shown in figure 13) is recommended in order to provide the need- ed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to con- nect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 13. supply voltage protection ai02169 v cc 0.1 m f device v cc v ss
M48T02, m48t12 16/19 part numbering table 12. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest you. example: m48t 02 C70 pc 1 tr device type m48t supply voltage and write protect voltage 02 = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 12 = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v speed C70 = 100ns (M48T02/12) C150 = 150ns (M48T02/12) C200 = 200ns (M48T02/12) package pc = pcdip24 temperature range 1 = 0 to 70c shipping method for soic blank = tubes tr = tape & reel
17/19 M48T02, m48t12 package mechanical information figure 14. pcdip24 C 24-pin plastic dip, battery caphat, package outline note: drawing is not to scale. table 13. pcdip24 C 24-pin plastic dip, battery caphat, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 34.29 34.80 1.350 1.370 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 25.15 30.73 0.990 1.210 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n24 24 pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3
M48T02, m48t12 18/19 revision history table 14. document revision history date revision details july 2000 first issue 07/13/00 t rec change (table 9) 05/07/01 reformatted; temp. / voltage info. added to tables (tables 4, 5, 7, 8, 9, 10) 05/14/01 note added to clock calibration section; table footnote correction (table 6) 07/16/01 basic formatting / content changes (figure 1, tables 4, 5, 10) 05/20/02 add countries to disclaimer 06/26/02 add footnote to table (table 10)
19/19 M48T02, m48t12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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